A conventional scheme of packaging a flip chip is shown in FIG. 1, where bumps 11 of flip chip 1 connect a surface 21 of substrate 2, a heat sink 3 includes a first portion 31 located above the heat dissipation surface 12 of flip chip 1, and a second portion 32 connected to the surface 21 through thermal paste 5, with heat sink 3 usually connected to surface 12 by adhesive material 4. The heat sink 3 in such a conventional package usually suffers warpage as shown in FIG. 2 when there arises thermal stress with the chip 1 in the package, and may even break away from flip chip 1 or substrate 2, resulting in very low adaptability of the package to environmental variation, and inevitably leading to extreme difficulty in predicting application reliability of the package product. Typical examples of this conventional scheme can be known from two prior arts: U.S. Pat. Nos. 5,724,729 and 5,587,882.
Although the prior art U.S. Pat. No. 5,311,402 differs from the aforementioned two prior arts, its scheme of integrating the so called "cap" and the substrate thereof is substantially similar to the aforementioned two prior arts, only with a difference that the cap thereof has its peripheral portion extending into the groove of the substrate thereof and being connected to the inner face of the groove through solder material. Such a package, when the chip therein suffers thermal stress, usually also has the cap thereof suffering warpage, resulting in low adaptability of the package to environmental variation, and inevitably leading to extreme difficulty in predicting application reliability of the package product.
To improve conventional schemes of packaging ICs including heat conducting promotion apparatus, the present invention suggests novel schemes of integrating heat conducting promotion apparatus (or those similar to the so called "cap" in U.S. Pat. No. 5,311,402) and substrates in packaging chips, enabling each manufacturer to select from among them the one most fitting individual conditions.